The wavelength switching performance of a super-structure-grating DBR laser (SSG-DBR-LD) has been investigated. The lasing wavelength could be selected by directly modulating the wavelength tuning region with the switching time of less than a few nanoseconds. We observed that the pulse width of the output signal in each lasing wavelength monotonically changed with increasing the injection current amplitude when the low level of injection current was fixed. This is considered to be due to the increase of transient time from high level to low level of injection current when the amplitude increases and time duration for carrier density to satisfy the lasing mode at the low level of injection current decreases. For improving the stability of the pulse width of the output signal, a novel method of the mean level of injection current pulse fixed is proposed. Almost the same pulse width for wavelength switching from one supermode to another has been realized because the low level of injection current becomes lower than the conventional method and the time duration for carrier density to satisfy the lasing mode at the low level of injection current increases.

Ultrahigh-speed all-optical label processing method is proposed and experimentally demonstrated. This processing method dramatically increases the label processing capability. Optical packet switch (OPS) systems and networks based on OPS nodes are applications of optical processing technologies. For the experiment, we constructed the world's first 40 Gbit/s/port OPS prototype with an all-optical label processor, optical switch, optical buffer, and electronic scheduler. Three-hop optical packet routing using OPS nodes was experimentally demonstrated with it, verifying the feasibility of OPS networks.

Packet loss is a serious problem due to the shortage of optical buffers in all-optical packet switched networks. In order to reduce packet losses, a dynamic routing method called 'deflection routing' has been proposed. Deflection routing, however, requires an optical switch to modify routing tables and packet labels for overflowing packets, so this routing method may also lead to other implementation problems in packet routing and forwarding. This paper proposes a simple routing method called 'reflection routing' which utilizes optical transport links as optical buffers to improve the quality of service in optical packet switched networks in terms of packet loss ratio. We numerically demonstrate the effectiveness and applicability of reflection routing.

We propose an optical packet switch (OPS) using a hybrid buffer structure for the contention resolution of asynchronous variable length packets. The hybrid buffer consists of a fiber delay line (FDL) buffer as the prime buffer and a shared electronic buffer as the supplementary buffer. For the performance evaluation, a modified void filling scheduling algorithm that can be applied to the OPS was proposed. Simulation results show that the use of the electronic buffer together with the FDL buffer significantly reduce the number of FDLs required for contention resolution and considerably lower packet loss.

A novel optical packet switch architecture is proposed that can support simultaneous processing and routing of packets in bands, without disturbing the granularity of the system. The packet router consists of a waveband converter and an AWG, combined in such a way that processing and switching of packets within and between the wavebands is allowed. The waveband converter is based on four-wave mixing in semiconductor optical amplifiers. Experimental results of the waveband conversion technique are presented to prove the feasibility of such a scheme. Simulation results of an 12 packet router are used to explain the operation of such a subsystem for a synchronous optical packet switched network.

This paper proposes Photonic Core Node based on a 2.56-Terabit/s opto-electronic switching fabric, which can economically handle the rapidly increasing multimedia traffics, such as Internet traffic. We have successfully developed the first prototype of Photonic Core Node. The prototype consists of a single-stage full-crossbar opto-electronic switching fabric, super-packet buffers for input queuing, and a desynchronized-round-robin scheduler. The switching fabric is upgradable up to 2.56 Tb/s, and employs wavelength-division-multiplexing techniques, which dramatically reduce the total number of optical switching elements down to one-eighth the number of those used in a conventional switching fabric. The super-packet buffer assembles 16 ATM cells routed to the same output port into a single fixed-length packet. The super-packet-switching scheme drastically reduces the overhead of optical switching from 32 to 2.9%, although it tends to decrease effective throughput. The desynchronized-round-robin scheduler maintains nearly 100% effective throughput for random traffic, recursively resolving the contention of connection requests in one scheduling routine while keeping fairness in a round robin manner. The proposed Photonic Core Node can accommodate not only ATM switching but also WDM optical path grooming/multiplexing, and IP routing by using IP input buffer interfaces, because optical switches are bit-rate/format-independent.

This paper proposes Photonic Core Node based on a 2.56-Terabit/s opto-electronic switching fabric, which can economically handle the rapidly increasing multimedia traffics, such as Internet traffic. We have successfully developed the first prototype of Photonic Core Node. The prototype consists of a single-stage full-crossbar opto-electronic switching fabric, super-packet buffers for input queuing, and a desynchronized-round-robin scheduler. The switching fabric is upgradable up to 2.56 Tb/s, and employs wavelength-division-multiplexing techniques, which dramatically reduce the total number of optical switching elements down to one-eighth the number of those used in a conventional switching fabric. The super-packet buffer assembles 16 ATM cells routed to the same output port into a single fixed-length packet. The super-packet-switching scheme drastically reduces the overhead of optical switching from 32 to 2.9%, although it tends to decrease effective throughput. The desynchronized-round-robin scheduler maintains nearly 100% effective throughput for random traffic, recursively resolving the contention of connection requests in one scheduling routine while keeping fairness in a round robin manner. The proposed Photonic Core Node can accommodate not only ATM switching but also WDM optical path grooming/multiplexing, and IP routing by using IP input buffer interfaces, because optical switches are bit-rate/format-independent.

A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)130 mm (D) 10 mm (H). Using the receiver module, a fast acquisition time of 9 bits and receiver sensitivity penalty of less than 1.5 dB due to re-synchronization were measured.

A novel 10-Gb/s fast acquisition bit-synchronization circuit for use in a Tb/s throughput optical packet switch has been developed. The circuit is a best-sampled-data-select type based on multiple phase-clocks, and it processes the asynchronous input packets into a synchronous data stream in a serial manner, which is advantageous in terms of circuit scale and consumption power compared with the parallel processing type. The circuit was developed using Si-bipolar ultrahigh-speed gate arrays and it was used to develop a 10-Gb/s optical asynchronous packet receiver module. The core logic of this circuit module required about 100 gates, consume 6 W, and the size of the module was reduced to only 170 mm (W)130 mm (D) 10 mm (H). Using the receiver module, a fast acquisition time of 9 bits and receiver sensitivity penalty of less than 1.5 dB due to re-synchronization were measured.